1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, relates to a semiconductor device having a high voltage MOSFET with very low on-resistance and method for fabricating the same.
2. Description of the Related Art
Bipolar-CMOS-LDMOSs (BCDs) have been widely used in power management integrated circuit (PMIC) applications. BCD technology integrates bipolar, complementary metal-oxide-semiconductor (CMOS) and laterally diffused metal-oxide-semiconductor (LDMOS) technology into one chip. In a BCD device, a bipolar device is used to drive high currents, a CMOS provides low power consumption for digital circuits, and a LDMOS device provides high voltage (HV) handling capabilities.
LDMOS devices are widely used in day to-day applications. On-resistance is an important factor that is directly proportional to the power consumption of an LDMOS device. As the demand for power savings and better performance of electronic devices increase, manufacturers have continuously sought to reduce the leakage and on-resistance (Ron) of LDMOS devices. However, the reduction of on-resistance is closely related to the high off-state breakdown voltage. Specifically, reducing the on-resistance leads to a substantial drop of the high off-state breakdown voltage. Thus, a conventional LDMOS device is able to deliver a high off-state breakdown voltage but fails to provide low on-resistance.
An LDMOS device includes a drift region, and a body region. It has been observed that the on-resistance of the conventional LDMOS device decreases when the dopant concentration of the drift region increases. However, the high off-state breakdown voltage of the LDMOS decreases as the doping concentration increases.
Thus, an improved semiconductor device and a method for fabricating the same are needed.